Xilinx Virtex-6 FPGA User Manual page 63

6.
7.
8.
9.
10. Wait for TXCTRLACK<n> to go High. The transmitter is ready for normal operation.
11. Change RXPOWERDOWN<n>[1:0] to 2'b00.
12. Wait for RXCTRLACK<n> to go High.
13. Pulse RXBUFRESET for one RXUSERCLKIN clock cycle. The receiver is ready for
X-Ref Target - Figure 2-8
T H R E S E T
T H I N I T
T H I N I T D O N E
T X P O W E R D O W N < n > [ 1 : 0 ]
T X B U F R E S E T < n >
T X C T R L A C K < n >
R X P O W E R D O W N < n > [ 1 : 0 ]
R X C T R L A C K < n >
R X B U F R E S E T < n >
Figure 2-8: GTH Transceiver Reset when in Full Line Rate Mode
Notes relevant to
1.
2.
Figure 2-9
GTHRESET when the GTH transceiver is configured in divided line rate mode (i.e., the
TXRATE<n>[1:0], SAMPLERATE<n>[2:0], and RXRATE<n>[1:0] ports are set to non-zero
values).
Follow these steps to initialize the GTH transceiver, when configured in divided line rate
mode:
1.
2.
3.
4.
5.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Wait for TXCTRLACK<n> and RXCTRLACK<n> from all four lanes to be deasserted
and then assert GTHINIT for 1 DCLK clock cycle.
Wait for GTHINITDONE to go High. The PLL is locked after GTHINITDONE is
asserted.
Pulse TXBUFRESET for one TXUSERCLKIN clock cycle.
Change TXPOWERDOWN<n>[1:0] to 2'b00 to power up the transmitter logic.
normal operation.
2 Õ b 1 0
( 1 )
2 Õ b 1 0
( 1 )
Figure 2-8:
The TXCTRLACK<n> and RXCTRLACK<n> signals at this time refer to all four lanes
within the Quad. The user must wait for all four TXCTRLACK<n> and
RXCTRLACK<n> signals to be deasserted before asserting GTHINIT.
The TXCTRLACK<n> and RXCTRLACK<n> signals can be High for more than
1 DCLK clock cycle.
shows the reset sequence of the GTH Quad following the assertion of
Set PCS_MODE_LANE<n>[7:4] and PCS_MODE_LANE<n>[3:0] to the datapath
mode used in the application for RX and TX, respectively.
Set PCS_RESET_LANE<n> to the datapath mode used in the application.
Set PCS_RESET_1_LANE<n> to the datapath mode used in the application.
Set TXPOWERDOWN<n>[1:0] and RXPOWERDOWN<n>[1:0] to 2'b10.
Set TXRATE<n>[1:0] and RXRATE<n>[1:0] to 2'b00, and set SAMPLERATE<n>[2:0]
to 3'b000.
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Reset and Initialization
2 Õ b 0 0
2 Õ b 0 0
U 3 7 1 _ c 2 _ 0 5 _ 0 8 0 8 0 9
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