Xilinx Virtex-6 FPGA User Manual page 58

Chapter 2: Shared Transceiver Features
Table 2-10: Reset Ports (Cont'd)
Port
TXPOWERDOWN0[1:0]
TXPOWERDOWN1[1:0]
TXPOWERDOWN2[1:0]
TXPOWERDOWN3[1:0]
TXRATE0[1:0]
TXRATE1[1:0]
TXRATE2[1:0]
TXRATE3[1:0]
TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
Notes:
1. <n> denotes lane 0, 1, 2, or 3.
58
Dir Clock Domain
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In TXUSERCLKIN0
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
In N/A
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Description
This control signal requests the transmitter power state:
00: Normal operation
10: Power off transmitter logic. The PLL continues to
operate in this state.
This port must always be set to 2'b10 during initialization
and when GTHRESET is asserted.
If the Quad is configured as a x4 link, only the port from
Lane 0 is valid.
This control signal specifies the transmitter lane divider
values:
00: Full data rate
10: 1/4 data rate
All other encodings are reserved.
This port must always be set to 2'b00 during initialization
and when GTHRESET is asserted.
This port provides a clock for the internal transmitter PCS
datapath. It is a buffered version of the
TXUSERCLKOUT<n>.
This clock must be stable for RXCTRLACK<n> and
RXRATE<n> ports to be active.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010