Xilinx Virtex-6 FPGA User Manual page 133

Table 4-21: FPGA RX Interface Ports (Cont'd)
Port Dir
RXDATA0[63:0] Out
RXDATA1[63:0]
RXDATA2[63:0]
RXDATA3[63:0]
RXUSERCLKIN0 In
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
RXUSERCLKOUT0 Out
RXUSERCLKOUT1
RXUSERCLKOUT2
RXUSERCLKOUT3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Clock Domain
RXUSERCLKIN0 This output bus is the receive data bus of the receive interface to the
FPGA.
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
N/A This port provides a clock for the internal receiver PCS datapath. It
is a buffered version of RXUSERCLKOUT<n>.
N/A This output is the recovered clock based on the receiver data bus
width and RXRATE<n>. This clock is used to drive
RXUSERCLKIN<n> through a buffer.
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FPGA RX Interface
Description
133