Xilinx Virtex-6 FPGA User Manual page 13

Figure 1-2
and shared resources for controlling and initializing the Quad.
X-Ref Target - Figure 1-2
TX3
PMA
RX3
GTH3
TX2
PMA
RX2
GTH2
PLL
REFCLK
TX1
PMA
RX1
GTH1
TX0
PMA
RX0
GTH0
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
shows a diagram of the GTH Quad, containing four GTH transceivers, a PLL,
PCS
PCS
Reset and
Power-Down
Controls
PCS
PCS
Figure 1-2: GTH Quad Block Diagram
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PCS to Fabric
Interface
PCS to Fabric
Interface
DRP Interface
Management
Interface Unit
PCS to Fabric
Interface
PCS to Fabric
Interface
GTH QUAD
Overview
Fabric Data,
Control, and
Clock for
GTH3
Fabric Data,
Control, and
Clock for
GTH2
Fabric Data,
Control, and
Clock for
GTH1
Fabric Data,
Control, and
Clock for
GTH0
UG371_c1_02_120809
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