Xilinx Virtex-6 FPGA User Manual page 127

Table 4-17: RX 8B/10B Block Ports (Cont'd)
Port
RXCTRL0[7:0]
RXCTRL1[7:0]
RXCTRL2[7:0]
RXCTRL3[7:0]
RXDATA0[63:0]
RXDATA1[63:0]
RXDATA2[63:0]
RXDATA3[63:0]
RXDISPERR0[7:0]
RXDISPERR1[7:0]
RXDISPERR2[7:0]
RXDISPERR3[7:0]
RXENCOMMADET0
RXENCOMMADET1
RXENCOMMADET2
RXENCOMMADET3
RXVALID0[7:0]
RXVALID1[7:0]
RXVALID2[7:0]
RXVALID3[7:0]
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Dir Clock Domain
Out RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
Out RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
Out RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
In RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
Out RXUSERCLKIN0
RXUSERCLKIN1
RXUSERCLKIN2
RXUSERCLKIN3
www.xilinx.com
Description
These outputs indicate the status of RXDATA<n> or they are used
as an extension of RXDATA<n> depending on the mode selected
in the receive datapath:
8B/10B: These outputs are asserted when RXDATA<n> is an
8B/10B K character.
RXCTRL<n>[7] corresponds to RXDATA<n>[63:56]
RXCTRL<n>[6] corresponds to RXDATA<n>[55:48]
RXCTRL<n>[5] corresponds to RXDATA<n>[47:40]
RXCTRL<n>[4] corresponds to RXDATA<n>[39:32]
RXCTRL<n>[3] corresponds to RXDATA<n>[31:24]
RXCTRL<n>[2] corresponds to RXDATA<n>[23:16]
RXCTRL<n>[1] corresponds to RXDATA<n>[15:8]
RXCTRL<n>[0] corresponds to RXDATA<n>[7:0]
64B/66B: These outputs are 64B/66B control bits.
Raw mode: These outputs are used as part of RXDATA<n>[71:64].
This output bus is the receive data bus of the receive interface to
the FPGA.
Used only for 8B/10B mode. These outputs indicate a disparity
error occurred on RXDATA<n>.
RXDISPERR<n>[7] corresponds to RXDATA<n>[63:56]
RXDISPERR<n>[6] corresponds to RXDATA<n>[55:48]
RXDISPERR<n>[5] corresponds to RXDATA<n>[47:40]
RXDISPERR<n>[4] corresponds to RXDATA<n>[39:32]
RXDISPERR<n>[3] corresponds to RXDATA<n>[31:24]
RXDISPERR<n>[2] corresponds to RXDATA<n>[23:16]
RXDISPERR<n>[1] corresponds to RXDATA<n>[15:8]
RXDISPERR<n>[0] corresponds to RXDATA<n>[7:0]
This input activates the comma detection and alignment circuit
for 8B/10B mode.
These status outputs indicate which bytes are valid used in
8B/10B mode only.
RXVALID<n>[7] corresponds to RXDATA<n>[63:56]
RXVALID<n>[6] corresponds to RXDATA<n>[55:48]
RXVALID<n>[5] corresponds to RXDATA<n>[47:40]
RXVALID<n>[4] corresponds to RXDATA<n>[39:32]
RXVALID<n>[3] corresponds to RXDATA<n>[31:24]
RXVALID<n>[2] corresponds to RXDATA<n>[23:16]
RXVALID<n>[1] corresponds to RXDATA<n>[15:8]
RXVALID<n>[0] corresponds to RXDATA<n>[7:0]
RX 8B/10B Block
127