Xilinx Virtex-6 FPGA User Manual page 50

Chapter 2: Shared Transceiver Features
The PLL output clock is used to generate the PCS clocks. There are three dividers to
generate different PCS clocks (see
•
•
•
Figure 2-5
PLLPCSCLKDIV ports determines the PCS clock frequency common across all the lanes in
the Quad. The SAMPLERATE port divides the Quad PCS clock and determine the internal
lane PCS clock for the each lane. The FABRIC_WIDTH attributes need to have correct
values to get the correct TXUSERCLKOUT and RXUSERCLKOUT values, depending on
the ratio between the FPGA logic data bus width and internal data bus width.
50
PLLPCSCLKDIV
SAMPLERATE (must have the same setting as TXRATE)
TX_FABRIC_WIDTH/RX_FABRIC_WIDTH
shows the relationship between the dividers in the PCS block. The
www.xilinx.com
Figure 2-5):
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010