Xilinx Virtex-6 FPGA User Manual page 107

Table 4-5
Table 4-5: RX Equalization Attributes
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
defines the RX equalization attributes.
Attribute
DFE_TRAIN_CTRL_LANE0
DFE_TRAIN_CTRL_LANE1
DFE_TRAIN_CTRL_LANE2
DFE_TRAIN_CTRL_LANE3
RX_AEQ_VAL0_LANE0
RX_AEQ_VAL0_LANE1
RX_AEQ_VAL0_LANE2
RX_AEQ_VAL0_LANE3
RX_AEQ_VAL1_LANE0
RX_AEQ_VAL1_LANE1
RX_AEQ_VAL1_LANE2
RX_AEQ_VAL1_LANE3
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Type
16-bit Hex This attribute controls the DFE.
[15]: 8B/10B mode and PRBS train_ok
qualifier for the DFE. This bit qualifies
train_ok signal from the 8B/10B and the
RX PRBS blocks. This bit defaults to 1'b1
for modes that use 8B/10B encoding or
PRBS.
[14]: Raw mode train_ok qualifier for the
DFE. This bit qualifies the train_ok signal
for Raw mode. This bit defaults to 1'b1 for
modes that do not use 8B/10B or 64B/66B
encoding or PRBS.
[13]: 64B/66B mode train_ok qualifier for
the DFE. This bit qualifies the train_ok
signal from the 64B/66B RX block. This bit
defaults to 1'b1 for modes that use
64B/66B encoding.
[12:0]: DFE train limit. These bits contain
the number (in 1K units) of consecutive
error-free symbols that must be received
before exiting DFE training mode. The
setting on these bits varies per mode:
• 64B/66B (use 10GBASE-KR as an
example): 13'h04C4
• 8B/10B: 13'h03D0
• PRBS: 13'h04C4
• Raw: If data encoding is similar to
64B/66B, use 13'h04C4. If data
encoding is similar to 8B/10B, use
13'h03D0.
16-bit Hex Reserved. Use the recommended values from
the Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from
the Virtex-6 FPGA GTH Transceiver Wizard.
RX Equalization
Description
107