Xilinx Virtex-6 FPGA User Manual page 15

Table 1-2
pins.
.
Table 1-2: GTH Analog Pin Summary
Notes:
1. These are power supply pins.
Table 1-3
Quad ports.
Table 1-3: GTH Quad Port Summary
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
lists alphabetically the signal names and directions of the GTH transceiver analog
(1)
MGTHAGND_[L,R]
(1)
MGTHAVCC_[L,R]
(1)
MGTHAVCCPLL_[L,R]
(1)
MGTHAVCCRX_[L,R]
(1)
MGTHAVTT_[L,R]
MGTRBIAS
MGTREFCLKP/MGTREFCLKN
MGTTXP0/MGTTXN0
MGTTXP1/MGTTXN1
MGTTXP2/MGTTXN2
MGTTXP3/MGTTXN3
MGTRXP0/MGTRXN0
MGTRXP1/MGTRXN1
MGTRXP2/MGTRXN2
MGTRXP3/MGTRXN3
lists alphabetically the signal names, directions, and clock domain of the GTH
Port
DADDR[15:0]
DCLK
DEN
DFETRAINCTRL0
DFETRAINCTRL1
DFETRAINCTRL2
DFETRAINCTRL3
DI[15:0]
DISABLEDRP
DRPDO[15:0]
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Pin
Dir
In
In
In
In
In
In
Out
Port and Attribute Summary
Dir
In
In
In
In
In
In
In
Out
In
Clock Domain
DCLK
N/A
DCLK
DCLK
DCLK
DCLK
DCLK
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