Xilinx Virtex-6 FPGA User Manual page 76

Chapter 3: Transmitter
The rate of the parallel clock, TXUSERCLKIN, at the interface is determined by the TX line
rate, the width of the TXDATA port, and whether or not 8B/10B mode is used. A block
inside the PCS handles the mapping of the internal data width to the fabric data width
selected in the design.
A data width converter block is included in the transmit datapath. This block includes:
•
•
•
The PCS_MODE_LANE<n>[3:0] attribute configures the internal data width, and the
TX_FABRIC_WIDTH<n> attribute configures the external data width.
how the interface width for the TX datapath is selected.
.
Table 3-2: FPGA TX Interface Datapath Configuration
Internal PCS Data
TX Data Mode
Width
8B/10B 20 bits
20 bits
20 bits
64B/66B 64 bits
Raw 16 bits
16 bits
16 bits
20 bits
20 bits
20 bits
76
A clock generator that takes the internal PCS clock and generates TXUSERCLKOUT
to the FPGA logic based on the external data width selected
A four-byte-deep FIFO that handles the phase difference between the internal PCS
clock and the external user clock
A data width converter between the internal PCS data interface and the external data
interface to the FPGA logic
Fabric Interface
Data Width
16 bits
32 bits
64 bits
64 bits
16 bits
32 bits
64 bits
20 bits
40 bits
80 bits
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PCS_MODE_LANE<n>[3:0]
0111
0111
0111
0001
1010
1010
1010
1011
1011
1011
Virtex-6 FPGA GTH Transceivers User Guide
Table 3-2 shows
TX_FABRIC_WIDTH<n>
16
32
64
6466
16
32
64
20
40
80
UG371 (v2.0) February 16, 2010