Xilinx Virtex-6 FPGA User Manual page 54

Chapter 2: Shared Transceiver Features
Table 2-8
Table 2-8: PLL Attributes
54
defines the PLL attributes.
Attribute
DLL_CFG0
DLL_CFG1
PLL_CFG0
PLL_CFG1
PLL_CFG2
RX_FABRIC_WIDTH0
RX_FABRIC_WIDTH1
RX_FABRIC_WIDTH2
RX_FABRIC_WIDTH3
TX_FABRIC_WIDTH0
TX_FABRIC_WIDTH1
TX_FABRIC_WIDTH2
TX_FABRIC_WIDTH3
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Type
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
[15:6]: Reserved
[5:0]: PLL feedback divider
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
Integer This attribute sets the mapping of the internal data
width (PCS) to the external data width (fabric) for
the receiver. Valid settings are:
"16" (DRP value 3'b000): PCS to Fabric 1:1
"20" (DRP value 3'b000): PCS to Fabric 1:1
"32" (DRP value 3'b011): PCS to Fabric 1:2 32 bit
"40" (DRP value 3'b101): PCS to Fabric 1:2 40 bit
"64" (DRP value 3'b010): PCS to Fabric 1:4 64 bit
"80" (DRP value 3'b110): PCS to Fabric 1:4 80 bit
"6466" (DRP value 3'b111): 64B/66B mode
Integer This attribute sets the mapping of the internal data
width (PCS) to the external data width (fabric) for
the transmitter. Valid settings are:
"16" (DRP value 3'b000): PCS to Fabric 1:1
"20" (DRP value 3'b000): PCS to Fabric 1:1
"32" (DRP value 3'b011): PCS to Fabric 1:2 32 bit
"40" (DRP value 3'b101): PCS to Fabric 1:2 40 bit
"64" (DRP value 3'b010): PCS to Fabric 1:4 64 bit
"80" (DRP value 3'b110): PCS to Fabric 1:4 80 bit
"6466" (DRP value 3'b111): 64B/66B mode
Virtex-6 FPGA GTH Transceivers User Guide
Description
UG371 (v2.0) February 16, 2010