Xilinx Virtex-6 FPGA User Manual page 77

Figure 3-1
different modes and the data converter block.
X-Ref Target - Figure 3-1
PMA
The user must consider these restrictions when configuring the fabric data width:
•
•
•
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
is a block diagram of the PCS logic. It shows the transmit datapath with the
20
8B/10B
16
64B/66B
16, 20
Raw
PRBS
16, 20
Checker
PRBS
16, 20
Generator
16, 20
Raw
16
64B/66B
20
8B/10B
PCS
Figure 3-1: PCS Block Diagram
The fabric interface data width must be the same for both the transmitter and receiver
within a GTH lane.
The data mode must be the same for both the transmitter and receiver within a GTH
lane.
The data mode must be the same on all four GTH lanes within a Quad.
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16
Receive
64
Data
Converter
16, 20
PCS to Fabric
Interface
16, 20
Transmit
64
Data
Converter
16
FPGA TX Interface
RXDATA[63:0]
RXCTRL[7:0]
RXCODEERR[7:0]
TXDATA[63:0]
TXCTRL[7:0]
TXDATAMSB[7:0]
UG371_c3_01_082709
77