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The mixer is a quatrature mixer, where an in-phase (I), and a quatrature
signal (Q) is obtained. Both signals are needed for the correlator, which
performs the basic digital signal processing. The I and Q-signals are buff-
ered with a first-in/first-out buffer (FIFO). The signal's echo strength, also
named relative signal strength (RSSI) is also low pass filtered and digitized.
The receiver power supply is under CPU control, and is powered by VCC.
Bi-directional digital bus transceivers provide the system bus interface
where the pre-processed data from the receiver are available for post proc-
essing by the CPU.
A-2.3
Timing Generator
The timing generator (TIMING-GEN) generates all signals needed for the
transmitter and receiver, such as the transmit signals, transmit enable, and
the local oscillator quatrature signal for the mixer.
The transmitter amplifier (XMT-AMP) is considered part of the timing
generator. It is a power driver, which buffers the logic level signal gener-
ated by the timing generator, and drives the transmitter output transformer
(XMT-XFMR). The transmit transformer provides isolation between the
Electronics Unit of the ADFM and the transducer; it connects to the trans-
ducer transmit input via a IS-barrier (optional). The transmit current is
monitored by a current transformer (CURR-XFMR). Its' output signal is
scaled and digitized, and is part of the ADFM's build in self test (BIT).
The timing generator interfaces to the system bus through bi-directional
digital bus transceivers. All timing generator setups are fully programma-
ble, and are downloaded by the CPU to the timing generator's own RAM.
The CPU is able to read back the timing setup data, the digitized current
sense data, as well as for monitoring purposes the unregulated DC input
voltage (VDC), the transmit voltage (VXMT), and the main 5 volt supply
(VDD1).
A-2.4
Central Processing Unit
The central processing unit (CPU) is not shown in detail in the block dia-
gram. The major CPU components are the micro processor unit (MPU),
random access memory (RAM) for data storage, read only memory (ROM)
for program storage, a real time clock (RTC) to keep time and date, a ad-
dress decoder, and a CPU supervisor.
The MPU is a power efficient 68000-based HCMOS processor. It provides
all housekeeping functions for the ADFM, as well as post processing of the
Doppler data, data formatting for data-I/O, and the user command input in-
terface.
ADFM Technical Manual (January 2000)
ADFM System Overview
page A-3
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