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TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
timing requirements for synchronous-burst SRAM cycles
NO.
6
t su(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high
7
t h(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high
† The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM
†‡
cycles
(see Figure 29 and Figure 30)
NO.
1
t d(EKOH-CEV) Delay time, ECLKOUT high to CEx valid
2
t d(EKOH-BEV) Delay time, ECLKOUT high to BEx valid
3
t d(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid
4
t d(EKOH-EAV) Delay time, ECLKOUT high to EAx valid
5
t d(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid
8
t d(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid
9
t d(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid
10
t d(EKOH-EDV) Delay time, ECLKOUT high to EDx valid
11
t d(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid
12
t d(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid
† The SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but
random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
74
SYNCHRONOUS-BURST MEMORY TIMING
PARAMETER
•
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
†
(see Figure 29)
GDPA-167
ZDPA−167
MIN
1.5
2.5
−200
UNIT
−250
MAX
ns
ns
GDPA-167
ZDPA−167
−200
UNIT
−250
MIN
MAX
1.2
7
ns
7
ns
1.2
ns
7
ns
1.2
ns
1.2
7
ns
1.2
7
ns
7
ns
1.2
ns
1.2
7
ns
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