Table of Contents
Advertisement
EDMA module and EDMA selector (continued)
Table 24. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3)
ESEL0 Register (0x01A0 FF00)
30 29
31
28 27
Reserved
R−0
14 13
15
12 11
Reserved
R−0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL1 Register (0x01A0 FF04)
30 29
31
28 27
Reserved
R−0
14 13
15
12 11
Reserved
R−0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL3 Register (0x01A0 FF0C)
30 29
31
28 27
Reserved
R−0
14 13
15
12 11
Reserved
R−0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 25. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description
BIT #
NAME
31:30
23:22
Reserved
15:14
7:6
29:24
21:16
EVTSELx
13:8
5:0
FLOATING POINT DIGITAL SIGNAL PROCESSOR
24 23
EVTSEL3
R/W−00 0011b
8 7
EVTSEL1
R/W−00 0001b
24 23
EVTSEL7
R/W−00 0111b
8 7
EVTSEL5
R/W−00 0101b
24 23
EVTSEL15
R/W−00 1111b
8 7
EVTSEL13
R/W−00 1101b
Reserved. Read-only, writes have no effect.
EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels.
The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These
EVTSELx fields are user−selectable. By configuring the EVTSELx fields to the EDMA selector value
of the desired EDMA sync event number (see Table 23), users can map any EDMA event to the
EDMA channel.
For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then
channel 15 is triggered by Timer0 TINT0 events.
•
POST OFFICE BOX 1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
22 21
Reserved
R−0
6 5
Reserved
R−0
22 21
Reserved
R−0
6
5
Reserved
R−0
22 21
Reserved
R−0
6 5
Reserved
R−0
DESCRIPTION
HOUSTON, TEXAS 77251−1443
TMS320C6711D
20 19
EVTSEL2
R/W−00 0010b
4 3
EVTSEL0
R/W−00 0000b
20 19
EVTSEL6
R/W−00 0110b
4 3
EVTSEL4
R/W−00 0100b
20 19
EVTSEL14
R/W−00 1110b
4 3
EVTSEL12
R/W−00 1100b
16
0
16
0
16
0
45
Advertisement
Table of Contents
