5−9 Synchronous Dram Cycle Timing Requirements; [Sdram Clock = 1X, (1/4)X, And (1/8)X Of Cpu Clock]; 5−10 Synchronous Dram Cycle Switching Characteristics [Sdram Clock = 1X, (1/4)X, And (1/8)X Of Cpu Clock]; Synchronous Dram (Sdram) Timings - Texas Instruments TMS320VC5509 Data Manual

Electrical Specifications

5.7.2 Synchronous DRAM (SDRAM) Timings

Table 5−9, Table 5−10, Table 5−11, and Table 5−12 assume testing over recommended operating conditions
(see Figure 5−8 through Figure 5−13).
Table 5−9. Synchronous DRAM Cycle Timing Requirements
NO.
M19 t su(DV-CLKMEMH)
M20 t h(CLKMEMH-DV)
M21 t c(CLKMEM)
† The EMIFX2 bit of the External Bus Selection Register (EBSR) is cleared. See Section 3.5.1, External Bus Selection Register, for more details.
‡ Maximum SDRAM operating frequency supported is 72 MHz.
Table 5−10. Synchronous DRAM Cycle Switching Characteristics
NO. NO.
M22 t d(CLKMEMH-CEL)
M23 t d(CLKMEMH-CEH)
M24 t d(CLKMEMH-BEV)
M25 t d(CLKMEMH-BEIV)
M26 t d(CLKMEMH-AV)
M27 t d(CLKMEMH-AIV)
M28 t d(CLKMEMH-SDCASL)
M29 t d(CLKMEMH-SDCASH)
M30 t d(CLKMEMH-DV)
M31 t d(CLKMEMH-DIV)
M32 t d(CLKMEMH-SDWEL)
M33 t d(CLKMEMH-SDWEH)
M34 t d(CLKMEMH-SDA10V)
M35 t d(CLKMEMH-SDA10IV)
M36 t d(CLKMEMH-SDRASL)
M37 t d(CLKMEMH-SDRASH)
† The EMIFX2 bit of the External Bus Selection Register (EBSR) is cleared. See Section 3.5.1, External Bus Selection Register, for more details.
84 SPRS163H

[SDRAM Clock = 1X, (1/4)X, and (1/8)X of CPU Clock]

Setup time, read data valid before CLKMEM high
Hold time, read data valid after CLKMEM high
Cycle time, CLKMEM
[SDRAM Clock = 1X, (1/4)X, and (1/8)X of CPU Clock]
PARAMETER PARAMETER
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address
valid
Delay time, CLKMEM high to address
invalid
Delay time, CLKMEM high to SDCAS low
Delay time, CLKMEM high to SDCAS
high
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SDWE low
Delay time, CLKMEM high to SDWE high
Delay time, CLKMEM high to SDA10
valid
Delay time, CLKMEM high to SDA10
invalid
Delay time, CLKMEM high to SDRAS low
Delay time, CLKMEM high to SDRAS
high
†
13.88 ‡
†
1X (1/4)X
CPU CLOCK CPU CLOCK
MIN MAX MIN MAX
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
1 6 21 26
1 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
0 6 21 26
April 2001 − Revised January 2008
MIN MAX UNIT
9 ns
0 ns
ns
(1/8)X
CPU CLOCK
UNIT UNIT
MIN MAX
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns
35 40 ns