Texas Instruments TMS320C6711D User Manual page 14

TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
peripheral register descriptions (continued)
For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2.
31
Word 0
Word 1
Word 2 Array/Frame Count (FRMCNT)
Word 3
Word 4 Array/Frame Index (FRMIDX)
Word 5 Element Count Reload (ELERLD)
Figure 2. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event
HEX ADDRESS RANGE
01A0 0800 − 01A0 FEFC
01A0 FF00
01A0 FF04
01A0 FF08 − 01A0 FF0B
01A0 FF0C
01A0 FF1F − 01A0 FFDC
01A0 FFE0
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
01A0 FFF8
01A0 FFFC
01A1 0000 − 01A3 FFFF
HEX ADDRESS RANGE
0200 0000
0200 0004
0200 0008
0200 000C
0200 0010
0200 0014 − 0200 001C
0200 0020
0200 0024
0200 0028
0200 002C
0200 0030
† All the QDMA and Pseudo registers are write-accessible only
14
EDMA Channel Options Parameter (OPT)
EDMA Channel Source Address (SRC)
EDMA Channel Destination Address (DST)
Table 8. EDMA Registers
ACRONYM
− Reserved
ESEL0 EDMA event selector 0
ESEL1 EDMA event selector 1
− Reserved
ESEL3 EDMA event selector 3
− Reserved
PQSR Priority queue status register
CIPR Channel interrupt pending register
CIER Channel interrupt enable register
CCER Channel chain enable register
ER Event register
EER Event enable register
ECR Event clear register
ESR Event set register
– Reserved
Table 9. Quick DMA (QDMA) and Pseudo Registers
ACRONYM
QOPT QDMA options parameter register
QSRC QDMA source address register
QCNT QDMA frame count register
QDST QDMA destination address register
QIDX QDMA index register
− Reserved
QSOPT QDMA pseudo options register
QSSRC QDMA pseudo source address register
QSCNT QDMA pseudo frame count register
QSDST QDMA pseudo destination address register
QSIDX QDMA pseudo index register
POST OFFICE BOX 1443
Element Count (ELECNT)
Element Index (ELEIDX)
Link Address (LINK)
REGISTER NAME
REGISTER NAME
•
HOUSTON, TEXAS 77251−1443
0 EDMA Parameter
OPT
SRC
CNT
DST
IDX
RLD
†