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PLL and PLL controller (continued)
PLLCSR Register (0x01B7 C100)
28 27
31
15
12 11
Reserved
R−0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
BIT #
NAME
31:7
Reserved
6
STABLE
5:4
Reserved
3
PLLRST
2
Reserved
1
PLLPWRDN
0
PLLEN
FLOATING POINT DIGITAL SIGNAL PROCESSOR
24 23
Reserved
R−0
8
7
6
STABLE
R−x
Table 29. PLL Control/Status Register (PLLCSR)
Reserved. Read-only, writes have no effect.
Oscillator Input Stable. This bit indicates if the OSCIN/CLKIN input has stabilized.
0 – OSCIN/CLKIN input not yet stable. Oscillator counter is not finished counting (default).
1 – OSCIN/CLKIN input stable.
Reserved. Read-only, writes have no effect.
Asserts RESET to PLL
0 – PLL Reset Released.
1 – PLL Reset Asserted (default).
Reserved. The user must write a "0" to this bit.
Select PLL Power Down
0 – PLL Operational (default).
1 – PLL Placed in Power-Down State.
PLL Mode Enable
0 – Bypass Mode (default). PLL disabled.
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
directly from input reference clock.
1 – PLL Enabled.
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
from PLL output.
•
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
20 19
5
4
3
Reserved
PLLRST
Reserved
R−0
RW−1
R/W−0
DESCRIPTION
TMS320C6711D
16
2
1
PLLPWRDN
PLLEN
R/W−0b
RW−0
0
49
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