Emif Device Speed - Texas Instruments TMS320C6711D User Manual

EMIF device speed

The maximum EMIF speed on the device is 100 MHz. TI recommends utilizing I/O buffer information
specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given
board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using
IBIS Models for Timing Analysis application report (literature number SPRA839).
For ease of design evaluation, Table 34 contains IBIS simulation results showing the maximum EMIF-SDRAM
interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be
performed to verify that all AC timings are met for the specified board layout. Other configurations are also
possible, but again, timing analysis must be done to verify proper AC timings.
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
BOARD CONFIGURATION
EMIF INTERFACE
TYPE
COMPONENTS
1-Load 1-Load One bank of one One bank of one
Short Traces 32-Bit SDRAM
2-Loads 2-Loads One bank of two One bank of two
Short Traces Short Traces 16-Bit SDRAMs 16-Bit SDRAMs
One bank of two One bank of two
3-Loads 3-Loads
32-Bit SDRAMs 32-Bit SDRAMs
Short Traces Short Traces
One bank of buffer One bank of buffer
One bank of one One bank of one
32-Bit SDRAM 32-Bit SDRAM
3-Loads 3-Loads
One bank of one One bank of one
Long Traces Long Traces
32-Bit SBSRAM
One bank of buffer
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing
requirements can be met for the particular system.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table 34. Example Boards and Maximum EMIF Speed
BOARD TRACE
1 to 3-inch traces with proper 1 to 3-inch traces with proper
termination resistors; termination resistors;
Trace impedance ~ 50 Ω Trace impedance ~ 50 Ω
1.2 to 3 inches from EMIF to 1.2 to 3 inches from EMIF to
each load, with proper each load, with proper
termination resistors; termination resistors;
Trace impedance ~ 78 Ω Trace impedance ~ 78 Ω
1.2 to 3 inches from EMIF to 1.2 to 3 inches from EMIF to
each load, with proper each load, with proper
termination resistors; termination resistors;
Trace impedance ~ 78 Ω Trace impedance ~ 78 Ω
4 to 7 inches from EMIF; 4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω Trace impedance ~ 63 Ω
•
POST OFFICE BOX 1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
SDRAM SPEED GRADE
143 MHz 32-bit SDRAM (−7)
166 MHz 32-bit SDRAM (−6)
183 MHz 32-bit SDRAM (−55)
200 MHz 32-bit SDRAM (−5)
125 MHz 16-bit SDRAM (−8E)
133 MHz 16-bit SDRAM (−75)
143 MHz 16-bit SDRAM (−7E)
167 MHz 16-bit SDRAM (−6A)
167 MHz 16-bit SDRAM (−6)
125 MHz 16-bit SDRAM (−8E)
133 MHz 16-bit SDRAM (−75)
143 MHz 16-bit SDRAM (−7E)
167 MHz 16-bit SDRAM (−6A)
167 MHz 16-bit SDRAM (−6)
143 MHz 32-bit SDRAM (−7)
166 MHz 32-bit SDRAM (−6)
183 MHz 32-bit SDRAM (−55)
200 MHz 32-bit SDRAM (−5)
HOUSTON, TEXAS 77251−1443
TMS320C6711D
MAXIMUM ACHIEVABLE MAXIMUM ACHIEVABLE
EMIF-SDRAM
INTERFACE SPEED
100 MHz
For short traces, SDRAM data
output hold time on these output hold time on these
SDRAM speed grades cannot
meet EMIF input hold time meet EMIF input hold time
requirement (see NOTE 1).
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
100 MHz
100 MHz
100 MHz
For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
83 MHz
83 MHz
83 MHz
SDRAM data output hold time
cannot meet EMIF input hold
requirement (see NOTE 1).
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