Texas Instruments TMS320C6711D User Manual page 27

PIN
NO.
SIGNAL SIGNAL
TYPE † TYPE †
NAME
GDP/
ZDP
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ¶ (CONTINUED)
HRDY H19 O
CE3 V6 O/Z
CE2 W6 O/Z
CE1 W18 O/Z
CE0 V17 O/Z
BE3 V5 O/Z
BE2 Y4 O/Z
BE1 U19 O/Z
BE0 V20 O/Z
HOLDA J18 O
HOLD J17 I
BUSREQ J19 O
ECLKIN Y11 I
ECLKOUT Y10 O/Z
ARE/SDCAS/
V11 O/Z
SSADS
AOE/SDRAS/
W10 O/Z
SSOE
AWE/SDWE/
V12 O/Z
SSWE
ARDY Y5 I
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
¶ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
IPD/ IPD/
IPU ‡ ‡
IPD Host ready (from DSP to host)
IPU
Memory space enables Memory space enables
IPU
• Enabled by bits 28 through 31 of the word address • Enabled by bits 28 through 31 of the word address
IPU
• Only one asserted during any external data access • Only one asserted during any external data access
IPU
IPU
Byte-enable control Byte-enable control
IPU
• Decoded from the two lowest bits of the internal address • Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory
Byte-write enables for most types of memory
IPU
• Can be directly connected to SDRAM read and write mask signal (SDQM)
Can be directly connected to SDRAM read and write mask signal (SDQM)
IPU
EMIF − BUS ARBITRATION ¶
IPU Hold-request-acknowledge to the host
IPU Hold request from the host
IPU Bus request output
EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL ¶
IPD External EMIF input clock source
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5])
EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal
from the clock generator (default).
EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock
IPD
source pin (ECLKIN)
EKEN = 0 – ECLKOUT held low
EKEN = 1 – ECLKOUT enabled to clock (default)
IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe
IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
IPU Asynchronous memory ready input
•
POST OFFICE BOX 1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
DESCRIPTION DESCRIPTION
HOUSTON, TEXAS 77251−1443
TMS320C6711D
27