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TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292 − OCTOBER 2005
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE †
HCS
HD[15:0] (input)
HRDY
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
HAS †
HCNTL[1:0]
HR/W
HHWIL
HSTROBE ‡
HCS
HD[15:0] (input)
HRDY
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
90
HOST-PORT INTERFACE TIMING (CONTINUED)
1
2
1
2
1
2
3
1st halfword
5
Figure 44. HPI Write Timing (HAS Not Used, Tied High)
19
11
10
11
10
11
10
3
18
1st half-word
5
Figure 45. HPI Write Timing (HAS Used)
•
POST OFFICE BOX 1443
1
1
1
4
14
12
13
2nd halfword
19
10
10
10
4
14
12
13
2nd half-word
HOUSTON, TEXAS 77251−1443
2
2
2
3
12
13
17
5
11
11
11
18
12
13
5
17
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