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switching characteristics over recommended operating conditions for CLKOUT2
(see Figure 23)
NO.
1
t c(CKO2)
Cycle time, CLKOUT2
2
t w(CKO2H)
Pulse duration, CLKOUT2 high
3
t w(CKO2L)
Pulse duration, CLKOUT2 low
4
t t(CKO2)
Transition time, CLKOUT2
† The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN.
‡ C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
CLKOUT2
switching characteristics over recommended operating conditions for CLKOUT3
(see Figure 24)
NO.
1
t c(CKO3)
Cycle time, CLKOUT3
2
t w(CKO3H)
Pulse duration, CLKOUT3 high
3
t w(CKO3L)
Pulse duration, CLKOUT3 low
4
t t(CKO3)
Transition time, CLKOUT3
5
t d(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid
† The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN.
‡ C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register. For more details, see
PLL and PLL controller.
CLKIN
CLKOUT3
NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
INPUT AND OUTPUT CLOCKS (CONTINUED)
PARAMETER
Figure 23. CLKOUT2 Timings
PARAMETER
1
3
2
Figure 24. CLKOUT3 Timings
POST OFFICE BOX 1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
1
4
2
3
5
4
4
•
HOUSTON, TEXAS 77251−1443
TMS320C6711D
†‡
GDPA-167
ZDPA−167
−200
UNIT
−250
MIN
MAX
C2 − 0.8
C2 + 0.8
ns
(C2/2) − 0.8
(C2/2) + 0.8
ns
(C2/2) − 0.8
(C2/2) + 0.8
ns
2
ns
4
†§
GDPA-167
ZDPA−167
−200
UNIT
−250
MIN
MAX
C3 − 0.9
C3 + 0.9
(C3/2) − 0.9
(C3/2) + 0.9
(C3/2) − 0.9
(C3/2) + 0.9
3
1.5
7.5
5
ns
ns
ns
ns
ns
69
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