Table of Contents
Advertisement
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE †
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
HAS †
HCNTL[1:0]
HR/W
HHWIL
HSTROBE ‡
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
HOST-PORT INTERFACE TIMING (CONTINUED)
1
2
1
2
1
2
3
7
1st halfword
5
6
Figure 42. HPI Read Timing (HAS Not Used, Tied High)
19
10
11
11
10
11
10
3
18
7
1st half-word
5
Figure 43. HPI Read Timing (HAS Used)
POST OFFICE BOX 1443
1
1
1
4
15
9
16
2nd halfword
8
8
10
10
10
4
15
9
16
2nd half-word
8
8
•
HOUSTON, TEXAS 77251−1443
TMS320C6711D
SPRS292 − OCTOBER 2005
2
2
2
3
15
9
5
17
5
17
19
11
11
11
18
15
9
17
5
17
5
89
Advertisement
Table of Contents
