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TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
PIN
NO.
SIGNAL
SIGNAL
TYPE †
TYPE †
NAME
GDP/
ZDP
HINT
J20
O
HCNTL1
G19
I
HCNTL0
G18
I
HHWIL
H20
I
HR/W
G20
I
HD15
B14
HD14 §
C14
HD13 §
A15
HD12 §
C15
HD11
A16
HD10
B16
HD9
C16
HD8 §
B17
I/O/Z
I/O/Z
HD7
A18
HD6
C17
HD5
B18
HD4 §
C19
HD3 §
C20
HD2
D18
HD1
D20
HD0
E20
HAS
E18
I
HCS
F20
I
HDS1
E19
I
HDS2
F18
I
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
§ To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-kΩ
pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.
¶ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
26
Terminal Functions (Continued)
IPD/
IPD/
IPU ‡
‡
HOST-PORT INTERFACE (HPI)
IPU
Host interrupt (from DSP to host)
IPU
Host control − selects between control, address, or data registers
IPU
Host control − selects between control, address, or data registers
IPU
Host half-word select − first or second half-word (not necessarily high or low order)
IPU
Host read or write select
Host-port data
IPU
• Used for transfer of data, address, and control
• Used for transfer of data, address, and control
• Also controls initialization of DSP modes at reset via pullup/pulldown resistors
IPU
− Device Endian mode (HD8)
− Device Endian mode (HD8)
0 –
Big Endian
IPU
1 −
1 −
Little Endian
Little Endian
IPU
EMIF Big Endian mode correctness (EMIFBE) (HD12)
EMIF Big Endian mode correctness (EMIFBE) (HD12)
0 –
The EMIF data will always be presented on the ED[7:0] side of the bus,
IPU
regardless of the endianess mode (Little/Big Endian).
regardless of the endianess mode (Little/Big Endian).
1 −
In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
IPU
present on the ED[7:0] side of the bus.
present on the ED[7:0] side of the bus.
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be present
IPU
on the ED[31:24] side of the bus [default].
on the ED[31:24] side of the bus [default].
IPU
This new functionality does not affect systems using the curent default value of HD12=1. For
This new functionality does not affect systems using the curent default value of HD12=1. For
IPU
more detailed information on the big endian mode correctness, see the EMIF Big Endian Mode
Correctness portion of this data sheet.
Correctness portion of this data sheet.
IPU
− Bootmode (HD[4:3])
− Bootmode (HD[4:3])
IPU
00 –
00 –
HPI boot/Emulation boot
HPI boot/Emulation boot
01 −
01 −
CE1 width 8-bit, Asynchronous external ROM boot with default timings
CE1 width 8-bit, Asynchronous external ROM boot with default timings
IPD
(default mode)
(default mode)
10 −
10 −
CE1 width 16-bit, Asynchronous external ROM boot with default timings
CE1 width 16-bit, Asynchronous external ROM boot with default timings
IPU
11 −
11 −
CE1 width 32-bit, Asynchronous external ROM boot with default timings
CE1 width 32-bit, Asynchronous external ROM boot with default timings
IPU
Other HD pins (HD [15:13, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs/IPDs). For proper de-
Other HD pins (HD [15:13, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs/IPDs). For proper de-
vice operation of the HD[14, 13, 11:9, 7, 1, 0], do not oppose these pins with external IPUs/IPDs
IPU
at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.
at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.
IPU
For more details, see the Device Configurations section of this data sheet.
IPU
Host address strobe
IPU
Host chip select
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ¶
IPU
Host data strobe 1
IPU
Host data strobe 2
•
POST OFFICE BOX 1443
DESCRIPTION
DESCRIPTION
HOUSTON, TEXAS 77251−1443
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