Texas Instruments TMS320C6711D User Manual page 41

CPU CSR register description (continued)
BIT # NAME
31:24 CPU ID
23:16 REVISION ID
15:10 PWRD
9 SAT
8 EN
7:5 PCC
4:2 DCC
1 PGIE
0 GIE
FLOATING POINT DIGITAL SIGNAL PROCESSOR
Table 18. CPU CSR Register Bit Field Description
CPU ID + REV ID. Read only.
Identifies which CPU is used and defines the silicon revision of the CPU. Identifies which CPU is used and defines the silicon revision of the CPU.
CPU ID + REVISION ID (31:16) are combined for a value of 0x0203
Control power-down modes. The values are always read as zero.
000000 = no power-down (default)
001001 = PD1, wake-up by an enabled interrupt
010001 = PD1, wake-up by an enabled or not enabled interrupt
011010 = PD2, wake-up by a device reset
011100 = PD3, wake-up by a device reset
Others = Reserved
Saturate bit.
Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can
be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC
instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after
a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.
Endian bit. This bit is read-only.
Depicts the device endian mode.
0 = Big Endian mode.
1 = Little Endian mode [default].
Program Cache control mode.
L1D, Level 1 Program Cache
000/010 = Cache Enabled / Cache accessed and updated on reads.
All other PCC values reserved.
Data Cache control mode.
L1D, Level 1 Data Cache
000/010 = Cache Enabled / 2-Way Cache
All other DCC values reserved
Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is
taken. Allows for proper nesting of interrupts.
0 = Previous GIE value is 0. (default)
1 = Previous GIE value is 1.
Global interrupt enable bit.
Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).
0 = Disables all interrupts (except the reset interrupt and NMI) [default]
1 = Enables all interrupts (except the reset interrupt and NMI)
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SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
DESCRIPTION
TMS320C6711D
41