Texas Instruments TMS320C6711D User Manual page 97

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
FSX
6
DX Bit 0
DR Bit 0
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
NO. NO.
4 t su(DRV-CKXH) Setup time, DR valid before CLKX high
5 t h(CKXH-DRV) Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
2
7
Bit(n-1)
4
Bit(n-1)
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
TMS320C6711D
SPRS292 − OCTOBER 2005
3
(n-2) (n-3) (n-4)
5
(n-2) (n-3) (n-4)
†‡
(see Figure 50)
GDPA-167
ZDPA−167
−200
−250
MASTER SLAVE
MIN MAX MIN
12 2 − 6P
4 5 + 12P
UNIT UNIT
MAX
ns
ns
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