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TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292 − OCTOBER 2005
switching characteristics over recommended operating conditions during host-port interface
†‡
cycles
(see Figure 42, Figure 43, Figure 44, and Figure 45)
NO.
Delay time, HCS to HRDY §
5
t d(HCS-HRDY)
t d(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high ¶
6
7
t d(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read
8
t d(HDV-HRDYL) Delay time, HD valid to HRDY low
9
t oh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high
15
t d(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance
16
t d(HSTBL-HDV)
Delay time, HSTROBE low to HD valid
t d(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high #
17
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
§ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
¶ This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
# This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
88
HOST-PORT INTERFACE TIMING (CONTINUED)
PARAMETER
•
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
GDPA−167
ZDPA−167
−200
UNIT
−250
MIN
MAX
1
12
ns
3
12
ns
2
ns
2P − 4
ns
3
12
ns
3
12
ns
3
12.5
ns
3
12
ns
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