Texas Instruments TMS320C6711D User Manual page 96

TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292 − OCTOBER 2005
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
NO.
NO.
4 t su(DRV-CKXH) Setup time, DR valid before CLKX high
5 t h(CKXH-DRV) Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0
NO. NO.
1 t h(CKXL-FXL)
2 t d(FXL-CKXH)
3 t d(CKXL-DXV)
6 t dis(CKXL-DXHZ)
7 t d(FXL-DXV)
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
96
†‡
(see Figure 49)
PARAMETER PARAMETER
Hold time, FSX low after CLKX
low ¶
Delay time, FSX low to CLKX high #
Delay time, CLKX low to DX valid
Disable time, DX high
impedance following last data bit
from CLKX low
Delay time, FSX low to DX valid
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
GDPA−167
ZDPA−167
−200
−250
MASTER
MIN MAX
12
4
GDPA−167
ZDPA−167
−200
−250
MASTER §
SLAVE
MIN MAX MIN
L − 2 L + 3
T − 2 T + 3
−3 4 6P + 2
−2 4 6P + 3
H − 2 H + 6.5 4P + 2
†‡
(see Figure 49)
UNIT
UNIT
SLAVE
MIN MAX
2 − 6P ns
5 + 12P ns
UNIT UNIT
MAX
ns
ns
10P + 17 ns
10P + 17 ns
8P + 17 ns