External Memory Interface Timing - Texas Instruments TMS320C3x User Manual

9.6 External Memory Interface Timing

9.6.1 Primary-Bus Cycles
This section discusses functional timing of operations on the primary bus and the
expansion bus, the two independent parallel buses or the 'C3x devices.
The parallel buses implement three mutually exclusive address spaces distin-
guished through the use of three separate control signals: STRB, MSTRB, and
IOSTRB. The STRB signal controls accesses on the primary bus, and the
MSTRB and IOSTRB signals control accesses on the expansion bus. Since
the two buses are independent, you can make two accesses in parallel.
With the exception of bank switching and the external HOLD function (discussed
later in this section), timing of primary bus cycles and MSTRB expansion bus
cycles are identical and are discussed collectively. The abbreviation (M)STRB is
used in references that pertain equally to STRB and MSTRB. Similarly, (X)R/W,
(X)A, (X)D, and (X)RDY are used to symbolize the equivalent primary and expan-
sion bus signals. The IOSTRB expansion bus cycles are timed differently and are
discussed independently.
All bus cycles comprise integral numbers of H1 clock cycles. One H1 cycle is
defined to be from one falling edge of H1 to the next falling edge of H1. For
full-speed (zero wait-state) accesses, writes require two H1 cycles and reads
require one cycle; however, if the read follows a write, the read requires two
cycles.This applies to both the primary bus and the MSTRB expansion bus
access.
Note: Posted Write
The data written to external memory by CPU or DMA is "latched" into the bus
logic, allowing the CPU to continue with internal operation. Consequently,
writes to external memory effectively require only one cycle if no accesses to
that interface are in progress. However, if the next DMA or CPU access is to
the same external bus, the DMA or CPU waits and the write is considered a
2-cycle operation. This is normally referred to as posted-write.
The following discussions pertain to zero wait-state accesses unless otherwise
specified.
TMS320C30 and TMS320C31 External-Memory Interface
External Memory Interface Timing
9-15