Texas Instruments TMS320C6711D User Manual page 52

TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
PLL and PLL controller (continued)
OSCDIV1 Register (0x01B7 C124)
28 27
31
14
15 12 11
OD1EN
R/W−1
Legend: R = Read only, R/W = Read/Write; -n = value after reset
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through
the PLL path.
BIT # NAME
31:16 Reserved
15 OD1EN
14:5 Reserved
4:0 OSCDIV1
52
24 23
Reserved
R−0
8 7
Reserved
R−0
Table 32. Oscillator Divider 1 Register (OSCDIV1)
Reserved. Read-only, writes have no effect.
Oscillator Divider 1 Enable.
0 – Oscillator Divider 1 Disabled.
1 – Oscillator Divider 1 Enabled (default).
Reserved. Read-only, writes have no effect.
Oscillator Divider 1 Ratio [default is /8 (0 0111)].
00000 = /1 10000 =
00001 = /2 10001 =
00010 = /3 10010 =
00011 = /4 10011 =
00100 = /5 10100 =
00101 = /6 10101 =
00110 = /7 10110 =
00111 = /8 10111 =
01000 = /9 11000 =
01001 = /10 11001 =
01010 = /11 11010 =
01011 = /12 11011 =
01100 = /13 11100 =
01101 = /14 11101 =
01110 = /15 11110
01111 = /16 11111
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20 19
5 4 3
DESCRIPTION
/17
/18
/19
/20
/21
/22
/23
/24
/25
/26
/27
/28
/29
/30
= /31
= /32
16
2 1 0
OSCDIV1
R/W−0 0111