Texas Instruments TMS320C6711D User Manual page 30

TMS320C6711D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
PIN
NO.
SIGNAL SIGNAL
TYPE † TYPE †
NAME
GDP/
ZDP
DR1 M2
DX1 L2
FSR1 M3
FSX1 L1
CLKS0 K3
CLKR0 H3
CLKX0 G3
DR0 J1
DX0 H2
FSR0 J3
FSX0 H1
CLKOUT2/
Y12
GP[2]
GP[7](EXT_INT7) E3
GP[6](EXT_INT6) D2
GP[5](EXT_INT5) C1
GP[4](EXT_INT4) C2
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
30
Terminal Functions (Continued)
IPD/ IPD/
IPU ‡ ‡
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) (CONTINUED)
Receive data
On this device, this pin does not have an internal pullup (IPU). For proper device operation,
I IPU the DR1 pin should either be driven externally at all times or be pulled up with a 10-kΩ resis-
tor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a
10-kΩ pullup resistor may be desirable even when an external device is driving the pin.
O/Z IPU Transmit data
I/O/Z IPD Receive frame sync
I/O/Z IPD Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
I IPD External clock source (as opposed to internal)
I/O/Z IPD Receive clock
I/O/Z IPD Transmit clock
I IPU Receive data
O/Z IPU Transmit data
I/O/Z IPD Receive frame sync
I/O/Z IPD Transmit frame sync
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) MODULE
For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin.
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal
from the clock generator) or this pin can be programmed as GP[2] (I/O/Z).
I/O/Z IPD
When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control
register (GBLCTL) controls the CLKOUT2 pin (All devices).
CLK2EN = 0:
CLK2EN = 1:
General-purpose input/output pins (I/O/Z) which also function as external General-purpose input/output pins (I/O/Z) which also function as external
interrupts interrupts
• Edge-driven
Edge-driven
I/O/Z I/O/Z IPU IPU
• Polarity independently selected via the External Interrupt Polarity Register • Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0]), in addition to the GPIO registers.
POST OFFICE BOX 1443
DESCRIPTION DESCRIPTION
CLKOUT2 is disabled
CLKOUT2 enabled to clock [default]
•
HOUSTON, TEXAS 77251−1443