Synchronous Burst Read Access (Timing Parameters In Clock Cycles); Ac Characteristics For Asynchronous Read Access - Texas Instruments OMAP36 Series Technical Reference Manual

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Figure 10-38. Synchronous Burst Read Access (Timing Parameters in Clock Cycles)
FCLK
ClkActivationTime = 1
CLK
AdvRdOffTime = 2
nADV
nCS
OeOnTime = 3
nOE
A/D bus Valid Address
10.1.6.1.2.2 GPMC Configuration for Asynchronous Read Access
The clock runs at 104 MHz ( f = 104 MHz; T = 9, 615 ns).
Table 10-20 shows the timing parameters (on the memory side) that determine the parameters on the
GPMC side.
Table 10-21 shows how to calculate timings for the GPMC using the memory parameters.
Figure 10-39 shows the asynchronous read access.
AC Read Characteristics on the
Memory Side
tCE
tAAVDS
tAVDP
tCAS
tOE
tOEZ
Use the following formula to calculate the RdCycleTime parameter for this typical access:
RdCycleTime = RdAccessTime + AccessCompletion = RdAccessTime + 1 clock cycle + tOEZ:
• First, on the memory side, the external memory makes the data available to the output bus. This is the
memory-side read access time defined in
address capture (nADV rising edge) and the data valid on the output bus.
The GPMC side requires some hold to allow the data to be captured correctly and the access to be
finished.
• To read the data correctly, the GPMC must capture it with enough data setup time; the GPMC module
captures the data on the next rising edge. This is access time on the GPMC side.
• There must also be a data hold time for correctly reading the data (checking that there is no nOE/nCS
deassertion while reading the data). This data hold time is 1 clock cycle (AccessTime + 1).
• To complete the access, nOE/nCS signals are driven to High-Z. AccessTime + 1 + tOEZ is the read
SWPU177N – December 2009 – Revised November 2010
Public Version
tIACC (access time on memory side)
CsReadOffTime = RdCycleTime
OeOffTime = RdCycleTime
Table 10-20. AC Characteristics for Asynchronous Read Access
Read Access time from nCS low
Address setup time to rising edge of nADV
nADV low time
nCS setup time to nADV
Output enable to output valid
Output enable to High-Z
Copyright © 2009–2010, Texas Instruments Incorporated
2nd burst access
AccessTime = 10
Data Setup
D0
Description
Table 10-20: the number of clock cycles between the
General-Purpose Memory Controller
RdCycleTime = 11
3rd last burst access
Access Completion
D1 D2 D3
Duration (ns)
80
3
6
0
6
7
Memory Subsystem
gpmc-038
2189