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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0
NO.
NO.
Hold time, FSX low
1
t h(CKXL-FXL)
after CLKX low ¶
Delay time, FSX low to CLKX high #
2
t d(FXL-CKXH)
3
t d(CKXH-DXV)
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit from
6
t dis(CKXL-DXHZ)
CLKX low
Disable time, DX high impedance following last data bit from
7
t dis(FXH-DXHZ)
FSX high
8
t d(FXL-DXV)
Delay time, FSX low to DX valid
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
CLKX
FSX
DX
Bit 0
DR
Bit 0
Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
FLOATING POINT DIGITAL SIGNAL PROCESSOR
†‡
(see Figure 48)
PARAMETER
PARAMETER
1
2
7
8
6
4
•
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
GDPA−167
ZDPA−167
MASTER §
MIN
MAX
T − 2
T + 3
L − 2
L + 3
−3
4
L − 2
L + 3
3
Bit(n-1)
(n-2)
(n-3)
5
Bit(n-1)
(n-2)
(n-3)
TMS320C6711D
SPRS292 − OCTOBER 2005
−200
UNIT
UNIT
−250
SLAVE
MIN
MAX
ns
ns
6P + 2
10P + 17
ns
ns
2P + 3
6P + 17
ns
4P + 2
8P + 17
ns
(n-4)
(n-4)
95
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