Adrv9001 Example Use Cases; Adrv9001 In A Single-Band 2Rt2R Fdd Type Small-Cell Application - Analog Devices ADRV9001 User Manual

UG-1828

ADRV9001 EXAMPLE USE CASES

The intention of this section is to provide the reader with the overall idea how ADRV9001 integrated transceiver can operate as an RF
front end in different applications. The provided list is not exhaustive, and there are other applications in which the ADRV9001 can serve.
Each example is accompanied with a table that explains the main limitations and highlights what the customer should look for when
implementing the ADRV9001 in the end application.

ADRV9001 IN A SINGLE-BAND 2RT2R FDD TYPE SMALL-CELL APPLICATION

ANTENNA A
A
DUPLEXER
B
ANTENNA B
A
DUPLEXER
B
RF I/O FUNCTIONALITY
Rx1A RF RECEPTION (DIVERSITY/MIMO)
Rx1B USED BY Tx1 INIT CALIBRATIONS
Rx2A RF RECEPTION (DIVERSITY/MIMO)
Rx2B USED BY Tx2 INIT CALIBRATIONS
Tx1 RF TRANSMISSION (DIVERSITY/MIMO)
Tx2 RF TRANSMISSION (DIVERSITY/MIMO)
With a minimum number of external components, the ADRV9001 transceiver can be used to build complete RF to bits signal chains that
can serve as the RF front end in small cell type applications. The ADRV9001 dual Rx and Tx signal chains allow the user to implement
MIMO or diversity in their system. The ADRV9001 internal AGC can be used to autonomously monitor and set appropriate gain levels
for Rx signal chains. For non-time critical FDD type applications, control of the ADRV9001 TRx can be done through API commands
that use the SPI interface.
PA
VGA
LPF
BPF FILTER
LNA
ATTENUATOR
BPF FILTER
LNA
ATTENUATOR
PA
LPF
VGA
Figure 3. ADRV9001 in Single-Band 2T2R FDD Type Small Cell Application
Rev. PrC | Page 10 of 338
BALUN Tx1
COUPLER
BALUN
Rx1A
BALUN
Rx1B
BALUN
EXT LO1
/2
RF PLL1
BALUN EXT LO2
/2
RF PLL2
BALUN
Rx2A
BALUN
Rx2B
COUPLER
BALUN
Tx2
AGPIOs AuxADC
Preliminary Technical Data
POWER IC
ADRV9001
Tx1
DATA
3/4/6/7/8/10
INT
QEC SSI
DAC
LOL
Rx1
DDC DATA
3/6/8
DEC
ADC SSI
QEC
DC
12/16
DGPIOs
4
Rx/Tx_ENABLE
GP_INT
3/4
SPI
RESET
Rx2
DDC DATA
3/6/8
DEC
ADC SSI
QEC
DC
Tx2
DATA
3/4/6/7/8/10
INT
SSI
DAC QEC
LOL
DEV_CLKL_OUT
MCS
BALUN
DEV_CLK
AuxDAC
FPGA
OR
BBP
VCXO