UG-1828
ADRV9001 IN TETRA TYPE PORTABLE RADIO APPLICATION
ANTENNA
RF SWITCH
COUPLER
ATTENUATOR
RF I/O
FUNCTIONALITY
Rx1A
RF RECEPTION
Rx1B
USED BY Tx DPD AND CALIBRATIONS
Tx1
RF TRANSMISSION
TETRA Type Portable Radio Overview
With a minimum number of external components, the ADRV9001 transceiver can be used to build complete RF-to-bits signal chain that
can serve as RF front end in TETRA type applications. Internal DPD block can be used to linearize external power amplifier and improve
overall system efficiency. For systems that demand superior LO phase noise performance, ADRV9001 allows user to apply eternal RF LO.
ADRV9001 internal AGC can be used to autonomously monitor and set appropriate gain level for Rx signal chain. For time critical TDD
type applications control of the ADRV9001 TRx can be done by toggling control lines. ADRV9001 can control external Rx/Tx switch
using its analog GPIOs as well as provide power amplifier bias voltage by utilizing AuxDAC outputs.
Table 5. Constrains and Limitations in TETRA Type Portable Radio Application
Functionality
Constrains and Limitations
LO Generation
In Portable Radio, TETRA type application, ADRV9001 can use its internal LO to generate RF LO1 for both uplink and
downlink. For applications with stringent RF LO requirements, the user can use external LO inputs. External LO1
operating at 2× RF LO can be used for both uplink and downlink.
RF Front End
For LO generation, the ADRV9001 uses internal VCO that generates a square wave type signal. A square wave LO
would produce harmonics. For example: depending of RF matching used on the RF ports user 2nd LO harmonic can
be as high as −50 dBc and 3rd harmonic can be as high as −9 dBc. Therefore, the RF filtering on the Rx and Tx path
must ensure that signals at the LO harmonic frequencies (up to 9th in some cases) are not affecting overall system
performance.
PA
LPF
TEMPERATURE
SENSOR
BPF FILTER
LNA
EXTERNAL
LO SOURCE
Figure 7. ADRV9001 in TETRA Type Portable Radio Application
Rev. PrC | Page 18 of 338
POWER IC
ADRV9001
VGA
BALUN
Tx1
BALUN
Rx1A
BALUN
Rx1B
BALUN
EXT LO1
/2
RF PLL1
BALUN
EXT LO2
/2
RF PLL2
AGPIOs
AuxADC
Preliminary Technical Data
Tx1
DATA
3/4/6/7/8/10
INT
SSI
DAC
QEC
LOL
DPD
Rx1
DDC
DATA
3/6/8
DEC
SSI
ADC
QEC
DC
14/16
DGPIOs
2
Rx/Tx_ENABLE
GP_INT
3/4
SPI
RESET
DEV_CLKL_OUT
MCS
BALUN
DEV_CLK
AuxDAC
FPGA
OR
BBIC
VCXO
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