Multichip Synchronization; Introduction; Theory Of Operation - Analog Devices ADRV9001 User Manual

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MULTICHIP SYNCHRONIZATION

INTRODUCTION

Multi-chip synchronization (MCS) is necessary when application requires deterministic latency between data paths, such as MIMO
applications, which will require multiple ADRV9001 devices. MCS is the solution for this problem to have the data in multiple channels
aligned in time. Certain applications not only require the delay to be deterministic but also require phase to be the same. ADRV9001 will
also support PLL phase synchronization as one of the operation modes.

THEORY OF OPERATION

Figure 81, illustrates the synchronization between multiple ADRV9001 devices using a shared input pin, MCS. The MCS signal is
generated by the external clock chip (for example, AD9528) using device clock DEV_CLK and captured by each ADRV900x device using
negative or positive edge of DEV_CLK to meet setup and hold time with good margins. Each ADRV900x device uses this sampled MCS
to synchronize all internally generated clocks which make them aligned between all devices internal clocks.
DEV_CLK
CLK PLL
SAMPLING
CLKGEN
DIVIDERS SAMPLING
SAMPLING
SAMPLING
ANALOG
Sampled MCS
MCS pulse signal will be sampled internally by ADRV9001 by the DEV_CLK signal rising or falling edge. Figure 82 shows the example
that MCS pulse being sampled by the rising edge of the DEV_CLK. This process guarantees that the sampled MCS signal, which is used
to synchronize all ADRV9001 devices are time aligned.
MCS
MCS
MCS
DIGITAL
MCS
DIGITAL CLOCK MCS
DIGITAL CLOCK
MCS
RX LVDS CLOCK MCS
RX LVDS CLOCK
ADRV900x (2)
Figure 81 Multi-chip Synchronization System Diagram
DEV_CLK
CLK PLL
CLKGEN
DIVIDERS
ANALOG
Rev. PrC | Page 88 of 338
Preliminary Technical Data
MCS_2
MCS GENERATION
MCS_1
CLOCK CHIP
CLK_2
CLK_1 CLOCK GENERATION
MCS
MCS
SAMPLING
MCS
SAMPLING
DIGITAL
MCS
DIGITAL CLOCK MCS
SAMPLING
DIGITAL CLOCK
MCS
RX LVDS CLOCK MCS
SAMPLING
RX LVDS CLOCK
ADRV900x (1)