Misaligned Data Transfers On 32-Bit Bus; Write Cycle - Intel 80386 Reference Manual

LOCAL BUS INTERFACE
Table 3-4. Misaligned Data Transfers on 32-Bit Bus
First Cycle:
Second Cycle:
Transfer Physical Address Byte Address Byte
Type Address Bus
Enables Bus Enables
Word
4N
+
3 4N
+
4 0 4N 3
Doubleword
4N
+
1 4N
+
4 0 4N 1-3
Doubleword 4N
+
2 4N
+
4 0-1 4N 2-3
Doubleword
4N
+
3 4N
+
4 0-2 4N 3
NOTE: 4N
=
Nth doubleword address
The sequence of signals for the non-pipelined cycle is as follows:
• The 80386 initiates the cycle by driving ADS# low. The states of the address bus
(A31-A2), byte enable pins (BE3#-BEO#), and bus status outputs (M/IO#, D/C#,
W /R#, and LOCK#) at the CLK2 edge when ADS# is sampled low determine the type.
of bus cycle to be performed. For a read cycle,
-W/R# is low
- M/IO# is high for a memory read, low for an I/O read
-For a memory read, D/C# is high if data is to be read, low if an instruction is to be
read. Immediate data is included in an instruction.
- LOCK# is low if the bus cycle is a locked cycle. Only a memory data read cycle (in a
read-modify-write sequence) can be locked. No other bus master should be permitted
to control the bus between two locked bus cycles.
The address bus, byte enable pins, and bus status pins (with the exception of ADS#)
remain active through the end of the read cycle.
• At the end of T2, READY # is sampled. If READY # is low, the 80386 reads the input
data on the data bus.
• If READY# is high; wait states (one CLK cycle) are added until READY# is sampled
low. READY # is sampled at the end of each wait state.
• Once READY# is sampled low, the 80386 reads the input data, and the read cycle termi-
nates. If a new bus cycle is pending, it begins on the next CLK cycle.
3.1.5 Write Cycle
Write cycles, like read cycles, are of two types: pipelined address and non-pipelined address.
Pipelined address cycles are described in Section 3.1.6.
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