Instruction Pipelining - Intel 80386 Reference Manual

CHAPTER 2
INTERNAL ARCHITECTURE
The internal architecture of the 80386 consists of six functional units that operate in
parallel. Fetching, decoding, execution, memory management, and bus accesses for several
instructions are performed simultaneously. This parallel operation is called pipelined
instruction processing. With pipelining, each instruction is performed in stages, and the
processing of several instructions at different stages may overlap as illustrated in
Figure 2-1. The six-stage pipelined processing of the 80386 results in higher performance
and an enhanced throughput rate over non-pipelined processors.
The six functional units of the 80386 are identified as follows:
• Bus Interface Unit
• Code Prefetch Unit
• Instruction Decode Unit
• Execution Unit
• Segmentation Unit
• Paging Unit
TYPICAL
PROCESSOR
80386
BUS UNIT
- - E L A P S E D T I M E - - - - - - - - - - - -. . _
EXECUTE 2
~~~~~-------r------~--------T_------~------.
DECODE
UNIT
""'=='""" ___ -'-___ '--__
--1. _ _ _ -'- ______ •
EXECUTION - - - - - - - - - - - - - - -
~EXECUTE
1 EXECUTE 2
UNIT
~JaI
---------------
EXECUTE 3
EXECUTE 4
I
:_-_-_~-_-~
MMU
~~~~-~~:~~~~~~_~~~-~~~""AD~~~R~&"MM~U~~
_________
~_AD_D_R_&_M_MU
___
~I~~~~~~~~~~~~
210760-11
Figure 2·1. Instruction Pipelining
2-1