Sun Microsystems Ultra 27 Service Manual page 115

BIOS Port 80 POST Code Checkpoints
TABLE B–1
Post Code
24
2A
2C
2E
31
33
37
38
39
3A
3B
3C
40
52
60
75
78
7C
84
85
87
Appendix B • BIOS POST Code Checkpoints
Description
Test F000h segment shadow to see whether it is read/writable or not. If test fails,
keep beeping the speaker.
Reserved.
Autodetect flash type to load appropriate flash R/W codes into the runtime area in
F000 for ESCD & DMI support.
Reserved.
Use walking 1as algorithm to check out interface in CMOS circuitry. Also, set
real-time clock power status, and then check for override.
Reserved.
Program chipset default values into chipset. Chipset default values are
MODBINable by OEM customers.
Reserved.
Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See
also POST 26h.
Reserved.
Detect CPU information including brand, SMI type (Cyrix or Intel), and CPU
level (586 or 686).
Reserved.
Reserved.
Initial interrupts vector table. All hardware interrupts are directed to
SPURIOUS_INT_HDLR and software interrupts to SPURIOUS_soft_HDLR.
Reserved.
Initial EARLY_PM_INIT switch.
Reserved.
Load keyboard matrix (notebook platform).
Reserved.
HPM initialization (notebook platform).
Reserved.
(Continued)
BIOS POST Code Checkpoints
115