Communication Description; Controller Antilock Brake Description - Chrysler Vehicle User Manual

8E - 2 ELECTRONIC CONTROL MODULES
COMMUNICATION (Continued)
average 10.4 Kilo-bits per second (Kbps). By compar-
ison, the prior two-wire Chrysler Collision Detection
(CCD) data bus system is designed to run at 7.8125
Kbps.
The voltage network used to transmit messages
requires biasing and termination. Each module on
the PCI data bus system provides its own biasing
and termination. Each module (also referred to as a
node) terminates the bus through a terminating
resistor and a terminating capacitor. There are two
types of nodes on the bus. The dominant node termi-
nates the bus through a 1 KW resistor and a 3300 pF
capacitor. The Powertrain Control Module (PCM) is
the only dominant node for the PCI data bus system.
A standard node terminates the bus through an 11
KW resistor and a 330 pF capacitor.
The modules bias the bus when transmitting a
message. The PCI bus uses low and high voltage lev-
els to generate signals. Low voltage is around zero
volts and the high voltage is about seven and one-
half volts. The low and high voltage levels are gener-
ated by means of variable-pulse width modulation to
form signals of varying length. The Variable Pulse
Width Modulation (VPWM) used in PCI bus messag-
ing is a method in which both the state of the bus
and the width of the pulse are used to encode bit
information. A zero bit is defined as a short low
pulse or a long high pulse. A one bit is defined as a
long low pulse or a short high pulse. A low (passive)
state on the bus does not necessarily mean a zero bit.
It also depends upon pulse width. If the width is
short, it stands for a zero bit. If the width is long, it
stands for a one bit. Similarly, a high (active) state
does not necessarily mean a one bit. This too depends
upon pulse width. If the width is short, it stands for
a one bit. If the width is long, it stands for a zero bit.
In the case where there are successive zero or one
data bits, both the state of the bus and the width of
the pulse are changed alternately. This encoding
scheme is used for two reasons. First, this ensures
that only one symbol per transition and one transi-
tion per symbol exists. On each transition, every
transmitting module must decode the symbol on the
bus and begin timing of the next symbol. Since tim-
ing of the next symbol begins with the last transition
detected on the bus, all of the modules are re-syn-
chronized with each symbol. This ensures that there
are no accumulated timing errors during PCI data
bus communication.
The second reason for this encoding scheme is to
guarantee that the zero bit is the dominant bit on
the bus. When two modules are transmitting simul-
taneously on the bus, there must be some form of
arbitration to determine which module will gain con-
trol. A data collision occurs when two modules are
transmitting different messages at the same time.
When a module is transmitting on the bus, it is read-
ing the bus at the same time to ensure message
integrity. When a collision is detected, the module
that transmitted the one bit stops sending messages
over the bus until the bus becomes idle.
Each module is capable of transmitting and receiv-
ing data simultaneously. The typical PCI bus mes-
sage has the following four components:
• Message Header - One to three bytes in length.
The header contains information identifying the mes-
sage type and length, message priority, target mod-
ule(s) and sending module.
• Data Byte(s) - This is the actual message that
is being sent.
• Cyclic Redundancy Check (CRC) Byte - This
byte is used to detect errors during a message trans-
mission.
• In-Frame Response (IFR) byte(s) - If a
response is required from the target module(s), it can
be sent during this frame. This function is described
in greater detail in the following paragraph.
The IFR consists of one or more bytes, which are
transmitted during a message. If the sending module
requires information to be received immediately, the
target module(s) can send data over the bus during
the original message. This allows the sending module
to receive time-critical information without having to
wait for the target module to access the bus. After
the IFR is received, the sending module broadcasts
an End of Frame (EOF) message and releases control
of the bus.
The PCI data bus can be monitored using the
DRBIII scan tool. It is possible, however, for the bus
to pass all DRBIII tests and still be faulty if the
voltage parameters are all within the specified range
and false messages are being sent.
CONTROLLER ANTILOCK
BRAKE
DESCRIPTION
The CAB operates the ABS system, and is separate
from other vehicle electrical circuits. The CAB is
located under the instrument panel to the right side
of the steering column. It is mounted to bracket with
one bolt. The bracket is mounted to the front upper
cowl panel.
TJ