System Control Block Status Word - Intel GD82559ER Datasheet

GD82559ER — Networking Silicon
MDI Control Register:
Receive DMA Byte Count:
Flow Control Register:
PMDR:
General Control:
General Status:
8.1.1

System Control Block Status Word

The System Control Block (SCB) Status Word contains status information relating to the
82559ER's Command and Receive units.
Bits
15
14
13
12
11
10
9
8
7:6
5:2
1:0
58
The MDI Control register allows the CPU to read and write
information from the PHY unit (or an external PHY component)
through the Management Data Interface.
The Receive DMA Byte Count register keeps track of how many
bytes of receive data have been passed into host memory via DMA.
This register holds the flow control threshold value and indicates
the flow control commands to the 82559ER.
The Power Management Driver Register provides an indication in
memory and I/O space that a wake-up interrupt has occurred. The
PMDR is described in further detail in
Management Driver Register" on page
The General Control register allows the 82559ER to enter the deep
power-down state and provides the ability to disable the Clockrun
functionality. The General Control register is described in further
detail in
The General Status register describes the status of the 82559ER's
duplex mode, speed, and link. The General Status register is
detailed in
Name
Command Unit (CU) Executed. The CX bit indicates that the CU has
CX
completed executing a command with its interrupt bit set.
Frame Received. The FR bit indicates that the Receive Unit (RU) has
FR
finished receiving a frame.
CU Not Active. The CNA bit is set when the CU is no longer active and in
CNA
either an idle or suspended state.
Receive Not Ready. The RNR bit is set when the RU is not in the ready
RNR state. This may be caused by an RU Abort command, a no resources
situation, or set suspend bit due to a filled Receive Frame Descriptor.
Management Data Interrupt. The MDI bit is set when a Management Data
Interface read or write cycle has completed. The management data interrupt
MDI
is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
Software Interrupt. The SWI bit is set when software generates an
SWI
interrupt.
ER Early Receive. The ER bit is used for early receive interrupts.
FCP Flow Control Pause. The FCP bit is used as the flow control pause bit.
Command Unit Status. The CUS field contains the status of the Command
CUS
Unit.
RUS Receive Unit Status. The RUS field contains the status of the Receive Unit.
Reserved These bits are reserved and should be set to 00b.
Section 8.1.12, "General Control Register" on page
Section 8.1.13, "General Status Register" on page
Description
Section 8.1.11, "Power
60.
61.
61.
Datasheet