10/100 Mbps Csma/Cd Unit - Intel GD82559ER Datasheet

GD82559ER — Networking Silicon
Note that word 0Ah contains several configuration bits. Bits from word 0Ah, FBh through FEh,
and certain bits from word 0Dh are described as follows:
Word
5:14
13
12
11
10:8
7
6
5
4:3
1
D 11:8
7:0
FBh - ALL
FEh
Note: The IA read from the EEPROM is used by the 82559ER until an IA Setup command is issued by
software. The IA defined by the IA Setup command overrides the IA read from the EEPROM.
4.5

10/100 Mbps CSMA/CD Unit

The 82559ER CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE
802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions such as
transmission, reception, collision handling, etc. The 82559ER CSMA/CD unit interfaces the
internal PHY unit through a standard Media Independent Interface (MII), as specified by IEEE
802.3, Chapter 22. This is a 10/100 Mbps mode in which the data stream is nibble-wide and the
serial clocks run at either 25 or 2.5 MHz.
30
Table 1. EEPROM Words Field Descriptions
Bits Name
Signature
Reserved
Reserved
Boot Disable
Revision ID
Reserved
Deep Power
Down
Reserved
Reserved
2
Standby Enable
0 Reserved
Reserved
Reserved
Reserved
The Signature field is a signature of 01b, indicating to the 82559ER that there is
a valid EEPROM present. If the Signature field is not 01b, the other bits are
ignored and the default values are used.
Reserved Default value is 0b.
This bit is reserved and should be set to 0b.
The Boot Disable bit disables the Expansion ROM Base Address Register (PCI
Configuration space, offset 30H) when it is set. Default value is 0b.
These three bits are used as the three least significant bits of the device
revision, if bits 15, 14, and 13 equal 011b and the ID was set as described in
Section 7.1.10, "PCI Subsystem Vendor ID and Subsystem ID Registers" on
page 53. The default value depends on the silicon revision.
Reserved and should be set to 0b
This bit is used as the Deep Power Down enable/disable bit. When the DPD bit
equals 0b, deep power down is enabled in the D3 power state while PME is
disabled. If the DPD bit equals 1b, deep power down is disabled in the D3
power state while PME is disabled.
Reserved and should be set to 0b.
These are reserved and should be set to 00b.
The Standby Enable bit enables the 82559ER to enter standby mode. When
this bit equals 1b, the 82559ER is able to recognize an idle state and can enter
standby mode (some internal clocks are stopped for power saving purposes).
The 82559ER does not require a PCI clock signal in standby mode. If this bit
equals 0b, the idle recognition circuit is disabled and the 82559ER always
remains in an active state. Thus, the 82559ER will always request PCI CLK
using the Clockrun mechanism.
Set this bit equal to 0b for compatibility.
Reserved.
Description
Datasheet