Control/Status Registers; Lan (Ethernet) Control/Status Registers - Intel GD82559ER Datasheet

8.

Control/Status Registers

8.1

LAN (Ethernet) Control/Status Registers

The 82559ER's Control/Status Register (CSR) is illustrated in the figure below.
D31
PMDR
NOTE: In
as the Power Management Driver Register.
SCB Status Word:
SCB Command Word:
SCB General Pointer:
PORT Interface:
Flash Control Register:
EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to
Datasheet
Upper Word
SCB Command Word
System Control Block General Pointer
EEPROM Control Register
Management Data Interface (MDI) Control Register
Receive Direct Memory Access Byte Count
Flow Control Register
Reserved
Figure 23. 82559ER Control/Status Register
Figure 23 above, SCB is defined as the System Control Block of the 82559ER, and PMDR is defined
The 82559ER places the status of its Command and Receive units
and interrupt indications in this register for the CPU to read.
The CPU places commands for the Command and Receive units in
this register. Interrupts are also acknowledged in this register.
The SCB General Pointer register points to various data structures
in main memory depending on the current SCB Command word.
The PORT interface allows the CPU to reset the 82559ER, force the
82559ER to dump information to main memory, or perform an
internal self test.
The Flash Control register allows the CPU to enable writes to an
external Flash.
an external EEPROM.
Networking Silicon — GD82559ER
D16 D15 Lower Word
SCB Status Word
PORT
Flash Control Register
General Status
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D0 Offset
00H
04H
08H
0CH
10H
14H
Early Receive Int 18H
General Control 1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
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