Intel GD82559ER Datasheet page 4

GD82559ER - Networking Silicon
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2 10BASE-T Functionality ................................................................................................... 41
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.3 Auto-Negotiation Functionality.......................................................................................... 43
6.3.1
6.3.2
6.4 LED Description................................................................................................................ 45
7. PCI CONFIGURATION REGISTERS ........................................................................................... 47
7.1 LAN (Ethernet) PCI Configuration Space ......................................................................... 47
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers................................. 53
7.1.11 Capability Pointer ............................................................................................. 53
7.1.12 Interrupt Line Register...................................................................................... 53
7.1.13 Interrupt Pin Register ....................................................................................... 54
7.1.14 Minimum Grant Register .................................................................................. 54
7.1.15 Maximum Latency Register.............................................................................. 54
7.1.16 Capability ID Register....................................................................................... 54
7.1.17 Next Item Pointer.............................................................................................. 54
7.1.18 Power Management Capabilities Register ....................................................... 54
7.1.19 Power Management Control/Status Register (PMCSR)................................... 55
7.1.20 Data Register ................................................................................................... 56
8. CONTROL/STATUS REGISTERS................................................................................................ 57
8.1 LAN (Ethernet) Control/Status Registers.......................................................................... 57
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
iv
100BASE-TX Transmit Blocks ......................................................................... 37
100BASE-TX Receive Blocks .......................................................................... 40
100BASE-TX Collision Detection ..................................................................... 41
100BASE-TX Link Integrity and Auto-Negotiation Solution.............................. 41
Auto 10/100 Mbps Speed Selection ................................................................. 41
10BASE-T Transmit Clock Generation............................................................. 41
10BASE-T Transmit Blocks.............................................................................. 42
10BASE-T Receive Blocks............................................................................... 42
10BASE-T Collision Detection.......................................................................... 43
10BASE-T Link Integrity ................................................................................... 43
10BASE-T Jabber Control Function ................................................................. 43
10BASE-T Full Duplex ..................................................................................... 43
Description ....................................................................................................... 44
Parallel Detect and Auto-Negotiation ............................................................... 44
PCI Vendor ID and Device ID Registers .......................................................... 47
PCI Command Register ................................................................................... 48
PCI Status Register.......................................................................................... 49
PCI Revision ID Register.................................................................................. 50
PCI Class Code Register ................................................................................. 50
PCI Cache Line Size Register.......................................................................... 50
PCI Latency Timer............................................................................................ 51
PCI Header Type.............................................................................................. 51
PCI Base Address Registers............................................................................ 51
System Control Block Status Word .................................................................. 58
System Control Block Command Word............................................................ 59
System Control Block General Pointer............................................................. 59
PORT ............................................................................................................... 59
Flash Control Register...................................................................................... 59
EEPROM Control Register............................................................................... 59
Management Data Interface Control Register.................................................. 59
Receive Direct Memory Access Byte Count..................................................... 60
Early Receive Interrupt..................................................................................... 60
Datasheet