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5.
GD82559ER Test Port Functionality
5.1
Introduction
The 82559ER's NAND-Tree Test Access Port (TAP) is the access point for test data to and from
the device. The port provides the ability to perform basic production level testing. The port pro-
vides two functions:
1) The the synchronous IC validation mode used in the production of the device. This mode gives
the signals their names (i.e TCK, Testability Port Clock).
2) In addition to the synchronous test mode, the 82559ER supports asynchonous testing modes.
These test modes support the validation of connections at the board level.
5.2
Asynchronous Test Mode
Four asynchronous test modes are supported for system level design use. The modes are selected
through the use of Test Port input pin in static combinations. The Test Port pins are: TEST, TI,
TEXEC and TCK. During normal operation the Test pin must be pulled down through a resistor
(pulling Test high enables the test mode). All other Port inputs may have a pull-down at the design-
ers discretion.
5.3
Test Function Description
The 82559 TAP mode supports several tests that can be used in board level design. These tests can
help in the verification of basic functionality. As well as test the integrity of solder connection on
the board. The tests are as follows:
5.4
85/85
The 85/85 test provides the same functionality to the board level designer as the Tristate mode.
This mode is normal used during chip the chip burn-in cycling. The 82559ER is placed in this
mode during the 85
TEXEC = '1, TI = '1
Datasheet
o
/85% humidity test cycling. Test Pin Combinations: TEST = '1, TCK = '0,
Networking Silicon — GD82559ER
33
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