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CLK
CLOCK
6MHZ
GENERATION
6/3 MHZ
NRST
3MHZ
RESET
RESET
GENERATION
750 ms
MCU / DCU
COMMAND PORT
4 X 8 MCU/R: DCU/W
4 X 8 DCU/R: MCU/W
DIP SWITCH
H
(4)
A
HAMMER
M
DRIVER
M
TEST PORT
E
R
D
R
I
V
(4)
HAMMER
E
DRIVER
R
STATUS PORT
I/O
(4)
COLOR
N/A
CONTROL
(4)
PORT
COM
DCU
I/F
HSC
Figure 2–15. Mechanism Control Unit (MCU) Block Diagram (1 of 2)
2–20
CLK
(16)
ADDR
Z–80
CPU
DATA
(8)
DECODE
CNTL
BUFFER
BD0–7
D
0
–7
BD0–7
Z–80 CTC
D4–7
BD0–3
D0–7
!/O AND
ADDRESS
DECODE
BUFFERED ADDRESS BUS
BUFFERED DATA BUS
B
U
RD
F
CNTLS
WR
F
AND
E
R
INTA
E
D
D
A
T
A
B
U
S
D
0
–7
CS
A0, A1
A0, A1
8254
TIMER
CS
CS
A0, A1
8254
TIMER
NUD/HRS
DCMOD
HAM
(16)
EPROM
36K X 8
(8)
MCU REC
D0–7
B
U
F
F
E
R
E
D
A
D
D
R
E
S
S
FIRE 0,1,2
B
U
S
Principles of Operation
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Troubleshooting
