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CLK
CLOCK
GENERATION
8/4/2 MHZ
NRST
2MHZ
4MHZ
RESET
RESET
GENERATION
370 ms
HALT
BAUD RATE
XTAL OSC
HOST
INTERFACES
RXD
CLK
DCD
DSR
CTS
TXD
RTS
HOST
RS–232
DTR
REVCHNL
RX CLK
TX CLK
EXT CLK
GND
IDB8–IDB1
8
PI
IDSTB
HOST
IDRQ
DATA
PRODUCTS
IRDY
CEN–
IONL
TRONICS
ICSTB
ICBUSY
IACK
ICPE
+5V
GND
NDAV
DSTBOUT
Figure 2–13. Data Control Unit (DCU) Block Diagram (1 of 2)
2–16
8MHZ
CLK
(23)
ADDR
NMC
68000
CPU
DATA
(16)
CNTL
H
O
S
T
D
M
DTACK
A
A
D
D
R
H
E
N
O
S
N
S
S
F
S
W
T
A
I
D
U
T
(18)
M
L
C
A
T
H
INTA INTERRUPT
INPUTS
HOST SERIAL I/F
AND INTERRUPT
CONTROLLER
(RS–232–DVRS/RCVRS)
68901
I/O
PARALLEL
POLARITY
I/F
IDS
CONTROL
SIGNALS
DATA
CONTROL CODE DETECT
LATCHING
ERROR
DELETE CODE DETECT
ADDRESS
DECODE
BUS
ARBITRATION
CONTROL
RD
CNTLS
WR
DECODE
AND
BUFFER
INTA
DMA HNDSHK
DTACK
GENERATOR
4MHZ
RR
SERIAL AND
PARALLEL
I/F DMA
CONTROLLER
68B44
PARITY CHECK
OVERRUN DETECT
ADDRESS BUS
EPROM
160K x 16
DATA BUS
ADDRESS BUS
NLOAD
DATA BUS
DMA
HNDSHK
2MHZ
BUS
ARBITRATION
Principles of Operation
(16)
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