Decoupling Guidelines; Vcc Decoupling; Vtt Decoupling; Front Side Bus Agtl+ Decoupling - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

Twenty two lands are specified as V
provides power to the I/O buffers. The platform must implement a separate supply for
these lands which meets the V
2.3

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the Dual-Core
Intel® Xeon® Processor 5200 Seriesis capable of generating large average current
swings between low and full power states. This may cause voltages on power planes to
sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage
(C ), such as electrolytic capacitors, supply voltage during longer lasting changes in
BULK
current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running
condition. Care must be taken in the baseboard design to ensure that the voltage
provided to the processor remains within the specifications listed in
to do so can result in timing violations or reduced lifetime of the component. For further
information and guidelines, refer to the appropriate platform design guidelines.
2.3.1 V Decoupling
CC
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large voltage swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in
and layout guidelines, refer to the appropriate platform design guidelines.
2.3.2 V Decoupling
TT
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
2.3.3

Front Side Bus AGTL+ Decoupling

The Dual-Core Intel® Xeon® Processor 5200 Series integrates signal termination on
the die, as well as a portion of the required high frequency decoupling capacitance on
the processor package. However, additional high frequency capacitance must be added
to the baseboard to properly decouple the return currents from the FSB. Bulk
decoupling must also be provided by the baseboard for proper AGTL+ bus operation.
Decoupling guidelines are described in the appropriate platform design guidelines.
16
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
specifications outlined in
TT
Table 2-12). For further information regarding power delivery, decoupling
, which provide termination for the FSB and
TT
Table 2-12.
Table 2-12. Failure