And Transient Tolerance Load Lines - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

3. The loadlines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands
and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
4. I values greater than 75A are not applicable for the Dual-Core Intel® Xeon® Processor E5200 Series.
CC
5. I values greater than 50A are not applicable for the Dual-Core Intel® Xeon® Processor L5200 Series.
CC
6. I values greater than 42A are not applicable for the Dual-Core Intel® Xeon® Processor L5238.
CC
Figure 2-5. Dual-Core Intel® Xeon® Processor E5200 Series V

and Transient Tolerance Load Lines

VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
32
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
0 5 10 15 20
V
CC
Typical
CC
Icc [A]
25 30 35 40 45
V
CC
Minimum
Static
50 55 60 65 70
V
CC
Maximum
75