Reserved, Unused, And Test Signals; Loadline Selection Truth Table For Ll_Id[1:0]; Market Segment Selection Truth Table For Ms_Id[1:0] - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
Table 2-4.

Loadline Selection Truth Table for LL_ID[1:0]

LL_ID1
0
0
1
1
Note: The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.
Table 2-5.

Market Segment Selection Truth Table for MS_ID[1:0]

MS_ID1
0
0
1
1
Note: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be
used for future processor compatibility or for keying.
2.6

Reserved, Unused, and Test Signals

All Reserved signals must remain unconnected. Connection of these signals to V
V , or to any other signal (including each other) can result in component malfunction
SS
or incompatibility with future processors. See
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noted in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TAP, CMOS Asynchronous inputs, and CMOS Asynchronous outputs do not include on-
die termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guidelines.
The TESTHI signals must be tied to the processor V
matched resistor has a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50Ω, then a value
between 40Ω and 60Ω is required.
LL_ID0
0 Reserved
1 Dual-Core Intel
Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon®
Processor 5400 Series
0 Reserved
1 Quad-Core Intel
MS_ID0
0 Dual-Core Intel® Xeon® Processor 5200 Series
1 Dual-Core Intel® Xeon® Processor 5100 series
0 Quad-Core Intel® Xeon® Processor 5300 series
1 Quad-Core Intel® Xeon® Processor 5400 Series
). Unused outputs can be left unconnected; however, this may
SS
Description
® ®
Xeon Processor 5100 series, Dual-Core Intel®
® ®
Xeon processor 5300 series
Description
Chapter 4 for a land listing of the
). For details see Table
TT
using a matched resistor, where a
TT
, V ,
CC TT
2-18.
21