Agtl+ Fsb Specifications; Agtl+ Bus Voltage Definitions; Fsb Differential Bclk Specifications - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet
Dual-core intel xeon processor 5200 series
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- Design manual (100 pages)
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2.14
AGTL+ FSB Specifications
Routing topologies are dependent on the processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines for specific
implementation details. In most cases, termination resistors are not required as these
are integrated into the processor silicon. See
not include on-die termination. Please refer to
Valid high and low levels are determined by the input buffers via comparing with a
reference voltage called GTLREF_DATA and GTLREF_ADD. GTLREF_DATA is the
reference voltage for the FSB 4X data signals, GTLREF_ADD is the reference voltage for
the FSB 2X address signals and common clock signals.
GTLREF_DATA and GTLREF_ADD specifications.
The AGTL+ reference voltages (GTLREF_DATA and GTLREF_ADD) must be generated
on the baseboard using high precision voltage divider circuits. Refer to the appropriate
platform design guidelines for implementation details.
Table 2-18. AGTL+ Bus Voltage Definitions
Symbol
GTLREF_DATA
GTLREF_ADD
R
TT
R
TT
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of V
3.
GTLREF_DATA and GTLREF_ADD is generated from V
resistors. The minimum and maximum specifications account for this resistor tolerance. Refer to the
appropriate platform design guidelines for implementation details. The V
specifications is the instantaneous V
4.
R
is the on-die termination resistance measured at V
TT
0.31*V
5.
This specified range is also applicable for the DP[3:0]# and DRDY# Common Clock signals. Refer to
Table 2-6
6.
The DP[3:0]# and DRDY# Common Clock signals are not included in this range. Refer to
Table 2-7
Table 2-19. FSB Differential BCLK Specifications (Sheet 1 of 2)
Symbol
V
L
V
H
V
CROSS(abs)
V
CROSS(rel)
Δ
VCROSS
36
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
Parameter
Data Bus Reference
Voltage
Address Bus Reference
Voltage
Termination
Resistance (pull up)
for Data Signals
Termination
Resistance (pull up)
for Common Clock and
Address Signals
TT
. R
is connected to V
on die. Refer to processor I/O Buffer Models for I/V characteristics.
TT
TT
TT
and
Table 2-7
for AGTL+ signal grouping and details on signals that include on-die termination
for AGTL+ signal grouping and details on signals that include on-die termination.
Parameter
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Relative Crossing Point
Range of Crossing
Points
Table 2-8
for details on which signals do
Table 2-18
Table 2-18
Min
Typ
0.98 *
0.667 *
0.667 * V
V
TT
TT
0.98 *
0.667 *
0.667 * V
V
TT
TT
43
49
40
49
.
TT
on the baseboard by a voltage divider of 1%
TT
.
of the AGTL+ output driver. Measured at
OL
Min
Typ
-0.150
0.0
0.660
0.710
0.250
0.350
0.250 +
N/A
0.550 +
0.5 *
(V
-
(V
Havg
0.700)
0.700)
N/A
N/A
for R
values.
TT
lists the
Max
Units
1.02*0.667
V
* V
TT
1.02*0.667
V
* V
TT
55
Ω
58
Ω
referred to in these
TT
Table 2-6
Max
Unit
Figure
Notes
0.150
V
2-10
0.850
V
2-10
0.550
V
2-10,
2-11
V
2-10,
3,8,9,11
0.5 *
2-11
-
Havg
0.140
V
2-10,
2-11
Notes
1
2, 3
2, 3
4, 5
4, 6
and
1
2,9
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